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tm 3-1 HI5805 12-bit, 5msps a/d converter the HI5805 is a monolithic, 12-bit, analog-to-digital converter fabricated in intersils hbc10 bicmos process. it is designed for high speed, high resolution applications where wide bandwidth and low power consumption are essential. the HI5805 is designed in a fully differential pipelined architecture with a front end differential-in-differential-out sample-and-hold (s/h). the HI5805 has excellent dynamic performance while consuming 300mw power at 5msps. the 100mhz full power input bandwidth is ideal for communication systems and document scanner applications. data output latches are provided which present valid data to the output bus with a latency of 3 clock cycles. the digital outputs have a separate supply pin which can be powered from a 3.0v to 5.0v supply. pinout HI5805 (soic) top view features sampling rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .5msps ?ow power internal sample and hold fully differential architecture full power input bandwidth . . . . . . . . . . . . . . . . . 100mhz low distortion internal voltage reference ttl/cmos compatible digital i/o digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 5v to 3.0v applications digital communication systems undersampling digital if document scanners additional reference documents - an9214 using intersil high speed a/d converters - an9707 using the HI5805eval1 evaluation board ordering information part number sample rate temp. range ( o c) package pkg. no. HI5805bib 5msps -40 to 85 28 ld soic (w) m28.3 HI5805eval1 25 evaluation board 28 27 26 25 24 23 22 21 20 19 18 17 16 15 clk dv cc1 v in+ v dc v rout v rin a gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 d0 d2 d3 d4 dv cc2 d gnd2 d6 d7 d8 d9 d1 d5 d gnd1 dv cc1 d gnd1 av cc a gnd av cc d10 d11 v in- data sheet february 1999 file number 3984.6 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright intersil corporation 2000
3-2 functional block diagram typical application schematic v dc v in + v in - bias 4-bit flash + - 4-bit dac 4-bit flash stage 4 stage 3 stage 1 av cc a gnd dv cc1 d gnd1 digital delay d11 (msb) d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) 4-bit flash + - 4-bit dac and digital error correction clock ref dv cc2 d gnd2 v rout clk v rin x8 x8 s/h v rin (12) HI5805 v rout (11) v in - (9) clk (1) d gnd1 (5) d gnd2 (21) d gnd1 (3) a gnd (13) (14) av cc (22) dv cc2 (17) d9 (18) d8 (19) d7 (20) d6 (23) d5 (24) d4 (25) d3 (26) d2 (27) d1 (lsb) (28) d0 as close to part as possible 10 f and 0.1 f caps are placed d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 bnc clock v in + 0.1 f 10 f 0.1 f 10 f + + a gnd (7) v in + (8) v in - d gnd a gnd (2) dv cc1 (4) dv cc1 v dc (10) (16) d10 d10 (msb) (15) d11 d11 (6) av cc +5v +5v HI5805
3-3 absolute maximum ratings thermal information supply voltage, av cc or dv cc to a gnd or d gnd . . . . . . . . . +6.0v d gnd to a gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3v digital i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .d gnd to dv cc analog i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a gnd to av cc operating conditions temperature range, HI5805bib . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 1) ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering, 10s). . . . . . . . . . . . .300 o c (soic - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?ations av cc = dv cc1 = dv cc2 = dv cc3 = +5.0v, f s = 5msps at 50% duty cycle, v rin = 3.5v, c l = 10pf, t a = -40 o c to 85 o c, differential analog input, typical values are test results at 25 o c, unless otherwise speci?d parameter test condition HI5805bib (-40 o c to 85 o c) units min typ max accuracy resolution 12 - - bits integral linearity error, inl f in = dc - 1 2 lsb differential linearity error, dnl (guaranteed no missing codes) f in = dc - 0.5 1 lsb offset error, v os f in = dc - 19 - lsb full scale error, fse f in = dc - 32 - lsb dynamic characteristics minimum conversion rate no missing codes - 0.5 - msps maximum conversion rate no missing codes 5 - - msps effective number of bits, enob f in = 1mhz 10.0 11 - bits signal to noise and distortion ratio, sinad f in = 1mhz - 68 - db signal to noise ratio, snr f in = 1mhz - 68 - db total harmonic distortion, thd f in = 1mhz - -80 - dbc 2nd harmonic distortion f in = 1mhz - -86 dbc 3rd harmonic distortion f in = 1mhz - -83 - dbc spurious free dynamic range, sfdr f in = 1mhz - 83 - dbc intermodulation distortion, imd f 1 = 1mhz, f 2 = 1.02mhz - -68 - dbc transient response - 1 - cycle over-voltage recovery 0.2v overdrive - 2 - cycle analog input maximum peak-to-peak differential analog input range (v in + - v in -) - 2.0 - v maximum peak-to-peak single-ended analog input range - 4.0 - v analog input resistance, r in (notes 2, 3) 1 - - m ? analog input capacitance, c in -10- pf analog input bias current, i b + or i b - (note 3) -10 - +10 a differential analog input bias current i b diff = (i b + - i b -) - 0.5 - a full power input bandwidth, fpbw - 100 - mhz analog input common mode voltage range (v in + + v in -)/2 differential mode (note 2) 1 2.3 4 v = rms signal rms noise + distortion -------------------------------------------------------------- = rms signal rms noise ------------------------------- HI5805
3-4 internal voltage reference reference output voltage, v rout (loaded) - 3.5 - v reference output current --1ma reference temperature coefficient - 200 - ppm/ o c reference voltage input reference voltage input, v rin - 3.5 - v total reference resistance, r l - 7.8 - k ? reference current - 450 - a dc bias voltage dc bias voltage output, v dc - 2.3 - v max output current (not to exceed) - - 1 ma digital inputs (clk) input logic high voltage, v ih 2.0 - - v input logic low voltage, v il - - 0.8 v input logic high current, i ih v clk = 5v - - 10.0 a input logic low current, i il v clk = 0v - - 10.0 a input capacitance, c in -7-pf digital outputs (d0-d11) output logic sink current, i ol v o = 0.4v (note 2) 1.6 - - ma dv cc3 = 3.0v, v o = 0.4v - 1.6 - ma output logic source current, i oh v o = 2.4v (note 2) -0.2 - - ma dv cc3 = 3.0v, v o = 2.4v - -0.2 - ma output capacitance, c out -5-pf timing characteristics aperture delay, t ap -5-ns aperture jitter, t aj - 5 - ps (rms) data output delay, t od -8-ns data output hold, t h -8-ns data latency, t lat for a valid sample (note 2) - - 3 cycles clock pulse width (low) 5msps clock 90 100 110 ns clock pulse width (high) 5msps clock 90 100 110 ns power supply characteristics total supply current, i cc v in + - v in - = 2v - 60 70 ma analog supply current, ai cc v in + - v in - = 2v - 46 - ma digital supply current, di cc1 v in + - v in - = 2v - 13 - ma output supply current, di cc2 v in + - v in - = 2v - 1 - ma power dissipation v in + - v in - = 2v - 300 350 mw offset error psrr, ? v os av cc or dv cc = 5v 5% - 2 - lsb gain error psrr, ? fse av cc or dv cc = 5v 5% - 30 - lsb notes: 2. parameter guaranteed by design or characterization and not production tested. 3. with the clock off (clock low, hold mode). electrical speci?ations av cc = dv cc1 = dv cc2 = dv cc3 = +5.0v, f s = 5msps at 50% duty cycle, v rin = 3.5v, c l = 10pf, t a = -40 o c to 85 o c, differential analog input, typical values are test results at 25 o c, unless otherwise speci?d (continued) parameter test condition HI5805bib (-40 o c to 85 o c) units min typ max HI5805
3-5 timing waveforms notes: 4. s n : n-th sampling period. 5. h n : n-th holding period. 6. b m, n : m-th stage digital output corresponding to n-th sampled input. 7. d n : final data output corresponding to n-th sampled input. figure 1. internal circuit timing figure 2. input-to-output timing analog input clock input input s/h 1st stage 2nd stage 3rd stage 4th stage data output s n-1 h n - 1 s n h n s n + 1 h n + 1 s n + 2 h n + 2 s n + 3 h n + 3 s n+4 h n + 4 s n + 5 h n + 5 s n + 6 h n + 6 b 1, n + 5 b 1, n + 4 b 1, n + 3 b 1, n + 2 b 1, n + 1 b 1, n b 1, n - 1 b 2, n - 2 b 3, n - 2 b 4, n - 3 d n - 3 b 2, n - 1 b 3, n - 1 b 4, n - 2 d n - 2 t lat d n - 1 b 4, n - 1 b 2, n b 3, n b 2, n + 1 b 3, n + 1 b 4, n d n d n + 1 b 4, n + 1 b 2, n + 2 b 2, n + 3 b 3, n + 2 b 4, n + 2 d n + 2 b 3, n + 3 b 2, n + 4 b 3, n + 4 b 4, n + 3 d n + 3 t od t h data n - 1 data n clock input data output 0.8v 2.0v 1.5v t ap analog input t aj 1.5v HI5805
3-6 typical performance curves figure 3. effective number of bits (enob) vs input frequency figure 4. signal to noise and distortion (sinad) vs input frequency figure 5. signal to noise ratio (snr) vs input frequency figure 6. total harmonic distortion (thd) vs input frequency figure 7. spurious free dynamic range (sfdr) vs input frequency figure 8. effective number of bits (enob) vs clock duty cycle and input frequency 10 input frequency (mhz) 100 11 10 9 8 7 6 5 1 enob f s = 5msps temperature = 25 o c 10 input frequency (mhz) 100 70 60 50 40 30 1 sinad (db) f s = 5msps temperature = 25 o c 10 input frequency (mhz) 100 70 60 50 40 30 1 snr (db) f s = 5msps temperature = 25 o c 10 input frequency (mhz) 100 -40 -50 -60 -70 -80 1 thd (dbc) f s = 5msps temperature = 25 o c 10 input frequency (mhz) 100 80 70 60 50 40 1 sfdr (dbc) f s = 5msps temperature = 25 o c 0.5 duty cycle (t clk-low /t clk ) 0.6 11 10 9 8 7 6 5 0.4 enob f s = 5msps temperature = 25 o c 50mhz 20mhz 10mhz 5mhz 100mhz 2mhz 1mhz HI5805
3-7 figure 9. effective number of bits (enob) vs temperature and input frequency figure 10. internal voltage reference output (vrout) vs temperature and load figure 11. power dissipation vs temperature figure 12. power supply current vs temperature figure 13. 2048 point fft spectral plot typical performance curves (continued) 20 temperature ( o c) 80 11 10 9 8 7 6 5 -40 enob 50mhz 20mhz 10mhz 5mhz 100mhz 2mhz -20 0 40 60 f s = 5msps 1mhz 20 temperature ( o c) 80 3.525 3.515 3.505 3.495 3.485 3.475 -40 v rout (v) v refnom -20 0 40 60 v refld 20 temperature ( o c) 80 306 304 302 300 298 296 -40 power dissipation (mw) -20 0 40 60 f s = 5msps v in + = v in - = v dc 20 temperature ( o c) 80 70 50 40 30 20 0 -40 current (ma) -20 0 40 60 60 10 f s = 5msps v in + = v in - = v dc d icc2 d icc1 a icc i tot -120 output level (db) 200 400 600 800 1000 -100 -80 -60 -40 -20 0 frequency bin f in = 1mhz, f s = 5msps HI5805
3-8 detailed description theory of operation the HI5805 is a 12-bit, fully-differential, sampling pipeline a/d converter with digital error correction. figure 14 depicts the circuit for the front end differential-in-differential-out sample- and-hold (s/h). the switches are controlled by an internal clock which is a non-overlapping two phase signal, f 1 and f 2 , derived from the master clock. during the sampling phase, f 1 , the input signal is applied to the sampling capacitors, c s . at the same time the holding capacitors, c h , are discharged to analog ground. at the falling edge of f 1 the input signal is sampled on the bottom plates of the sampling capacitors. in the next clock phase, f 2 , the two bottom plates of the sampling capacitors are connected together and the holding capacitors are switched to the op-amp output nodes. the charge then redistributes between c s and c h completing one sample- and-hold cycle. the output is a fully-differential, sampled-data representation of the analog input. the circuit not only performs the sample-and-hold function but will also convert a single-ended input to a fully-differential output for the converter core. during the sampling phase, the v in pins see only the on-resistance of a switch and c s . the relatively small values of these components result in a typical full power input bandwidth of 100mhz for the converter. as illustrated in the functional block diagram and the timing diagram in figure 1, three identical pipeline subconverter stages, each containing a four-bit flash converter, a four-bit digital-to-analog converter and an amplifier with a voltage gain of 8, follow the s/h circuit with the fourth stage being only a 4-bit flash converter. each converter stage in the pipeline will be sampling in one phase and amplifying in the other clock phase. each individual sub-converter clock signal is offset by 180 degrees from the previous stage clock signal, with the result that alternate stages in the pipeline will perform the same operation. the 4-bit digital output of each stage is fed to a digital delay line controlled by the internal clock. the purpose of the delay line is to align the digital output data to the corresponding sampled analog input signal. this delayed data is fed to the digital error correction circuit which corrects the error in the output data with the information contained in the redundant bits to form the ?al 12-bit output for the converter. because of the pipeline nature of this converter, the data on the bus is output at the 3rd cycle of the clock after the analog sample is taken. this delay is specified as the data latency. after the data latency time, the data representing each succeeding sample is output at the following clock pulse. the output data is synchronized to the external clock by a latch. the digital outputs are in offset binary format (see table 1). internal reference generator, v rout and v rin the HI5805 has an internal reference generator, therefore, no external reference voltage is required. v rout must be connected to v rin when using the internal reference voltage. the HI5805 can be used with an external reference. the converter requires only one external reference voltage connected to the v rin pin with v rout left open. the HI5805 is tested with v rin equal to 3.5v. internal to the converter, two reference voltages of 1.3v and 3.3v are generated for a fully differential input signal range of 2v. in order to minimize overall converter noise, it is recommended that adequate high frequency decoupling be provided at the reference voltage input pin, v rin . pin descriptions pin no. name description 1 clk input clock. 2dv cc1 digital supply (5.0v). 3d gnd1 digital ground. 4dv cc1 digital supply (5.0v). 5d gnd1 digital ground 6av cc analog supply (5.0v). 7a gnd analog ground. 8v in + positive analog input. 9v in - negative analog input. 10 v dc dc bias voltage output. 11 v rout reference voltage output. 12 v rin reference voltage input. 13 a gnd analog ground. 14 av cc analog supply (5.0v). 15 d11 data bit 11 output (msb). 16 d10 data bit 10 output. 17 d9 data bit 9 output. 18 d8 data bit 8 output. 19 d7 data bit 7 output. 20 d6 data bit 6 output. 21 d gnd2 digital output ground. 22 dv cc2 digital output supply (3.0v to 5.0v). 23 d5 data bit 5 output. 24 d4 data bit 4 output. 25 d3 data bit 3 output. 26 d2 data bit 2 output. 27 d1 data bit 1 output. 28 d0 data bit 0 output (lsb). c h c s c s v in + v out + v out - v in - 1 1 2 1 1 c h 1 1 figure 14. analog input sample-and-hold + - - + HI5805
3-9 analog input, differential connection the analog input to the HI5805 can be con?ured in various ways depending on the signal source and the required level of performance. a fully differential connection (figure 15) will give the best performance for the converter. since the HI5805 is powered off a single +5v supply, the analog input must be biased so it lies within the analog input common mode voltage range of 1.0v to 4.0v. the performance of the adc does not change signi?antly with the value of the analog input common mode voltage. a 2.3v dc bias voltage source, v dc , half way between the top and bottom internal reference voltages, is made available to the user to help simplify circuit design when using a differential input. this low output impedance voltage source is not designed to be a reference but makes an excellent bias source and stays within the analog input common mode voltage range over temperature. the difference between the converters two internal voltage references is 2v. for the ac coupled differential input, (figure 15), if v in is a 2v p-p sinewave with -v in being 180 degrees out of phase with v in , then v in + is a 2v p-p sinewave riding on a dc bias voltage equal to v dc and v in -isa2v p-p sinewave riding on a dc bias voltage equal to v dc . consequently, the converter will be at positive full scale, all 1s digital data output code, when the v in + input is at v dc +1v and the v in - input is at v dc -1v (v in +-v in - = 2v). conversely, the adc will be at negative full scale, all 0s digital data output code, when the v in + input is equal to v dc - 1v and v in - is at v dc +1v (v in +-v in - = -2v). from this, the converter is seen to have a peak-to-peak differential analog input voltage range of 2v. the analog input can be dc coupled (figure 16) as long as the inputs are within the analog input common mode voltage range (1.0v vdc 4.0v). the resistors, r, in figure 16 are not absolutely necessary but may be used as load setting resistors. a capacitor, c, connected from v in + to v in - will help ?ter any high frequency noise on the inputs, also improving performance. values around 20pf are suf?ient and can be used on ac coupled inputs as well. note, however, that the value of capacitor c chosen must take into account the highest frequency component of the analog input signal. analog input, single-ended connection the con?uration shown in figure 17 may be used with a single ended ac coupled input. suf?ient headroom must be provided such that the input voltage never goes above +5v or below a gnd . table 1. code center description differential input voltage ? (using internal reference) offset binary output code msb lsb d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 +full scale (+fs) - 1 / 4 lsb +1.99976v 1 1 1 1 1 1 1 1 1 1 1 1 +fs - 1 1 / 4 lsb 1.99878v 1 1 1 1 1 1 1 1 1 1 1 0 + 3 / 4 lsb 732.4 v 1 0 0 0 0 000000 0 - 1 / 4 lsb -244.1 v 0 1 1 1 1 111111 1 -fs + 1 3 / 4 lsb -1.99829v 0 0 0 0 0 0 0 0 0 0 0 1 -full scale (-fs) + 3 / 4 lsb -1.99927v 0 0 0 0 0 0 0 0 0 0 0 0 ? the voltages listed above represent the ideal center of each offset binary output code shown. v in + v dc v in - HI5805 v in - v in figure 15. ac coupled differential input v in + v dc v in - HI5805 v in - v in r r c vdc vdc figure 16. dc coupled differential input HI5805
3-10 again, the difference between the two internal voltage references is 2v. if v in is a 4v p-p sinewave, then v in + is a 4v p-p sinewave riding on a positive voltage equal to vdc. the converter will be at positive full scale when v in + is at vdc + 2v (v in +-v in - = 2v) and will be at negative full scale when v in + is equal to vdc - 2v (v in + - v in - = -2v). in this case, v dc could range between 2v and 3v without a signi?ant change in adc performance. the simplest way to produce vdc is to use the v dc bias voltage output of the HI5805. the single ended analog input can be dc coupled (figure 18) as long as the input is within the analog input common mode voltage range. the resistor, r, in figure 18 is not absolutely necessary but may be used as a load setting resistor. a capacitor, c, connected from v in + to v in - will help ?ter any high frequency noise on the inputs, also improving performance. values around 20pf are suf?ient and can be used on ac coupled inputs as well. note, however, that the value of capacitor c chosen must take into account the highest frequency component of the analog input signal. a single ended source will give better overall system performance if it is ?st converted to differential before driving the HI5805. digital i/o and clock requirements the HI5805 provides a standard high-speed interface to external ttl/cmos logic families. the digital cmos clock input has ttl level thresholds. the low input bias current allows the HI5805 to be driven by cmos logic. the digital cmos outputs have a separate digital supply. this allows the digital outputs to operate from a 3.0v to 5.0v supply. when driving cmos logic, the digital outputs will swing to the rails. when driving standard ttl loads, the digital outputs will meet standard ttl level requirements even with a 3.0v supply. in order to ensure rated performance of the HI5805, the duty cycle of the clock should be held at 50% 5%. it must also have low jitter and operate at standard ttl levels. performance of the HI5805 will only be guaranteed at conversion rates above 0.5msps. this ensures proper performance of the internal dynamic circuits. supply and ground considerations the HI5805 has separate analog and digital supply and ground pins to keep digital noise out of the analog signal path. the part should be mounted on a board that provides separate low impedance connections for the analog and digital supplies and grounds. for best performance, the supplies to the HI5805 should be driven by clean, linear regulated supplies. the board should also have good high frequency decoupling capacitors mounted as close as possible to the converter. if the part is powered off a single supply then the analog supply and ground pins should be isolated by ferrite beads from the digital supply and ground pins. refer to the application note an9214, ?sing intersil high speed a/d converters?for additional considerations when using high speed converters. static performance de?itions offset error (v os ) the midscale code transition should occur at a level 1 / 4 lsb above half scale. offset is de?ed as the deviation of the actual code transition from this point. full-scale error (fse) the last code transition should occur for an analog input that is 3 / 4 lsb below positive full scale with the offset error removed. full-scale error is de?ed as the deviation of the actual code transition from this point. differential linearity error (dnl) dnl is the worst case deviation of a code width from the ideal value of 1 lsb. integral linearity error (inl) inl is the worst case deviation of a code center from a best ? straight line calculated from the measured data. power supply rejection ratio (psrr) each of the power supplies are moved plus and minus 5% and the shift in the offset and gain error (in lsbs) is noted. v in + v in - HI5805 v in vdc figure 17. ac coupled single ended input v in + v in - HI5805 v dc r c v in v dc figure 18. dc coupled single ended input HI5805
3-11 dynamic performance de?itions fast fourier transform (fft) techniques are used to evaluate the dynamic performance of the HI5805. a low distortion sine wave is applied to the input, it is coherently sampled, and the output is stored in ram. the data is then transformed into the frequency domain with an fft and analyzed to evaluate the dynamic performance of the a/d. the sine wave input to the part is -0.5db down from full scale for all these tests. snr and sinad are quoted in db. the distortion numbers are quoted in dbc (decibels with respect to carrier) and do not include any correction factors for normalizing to full scale. signal-to-noise ratio (snr) snr is the measured rms signal to rms noise at a speci?d input and sampling frequency. the noise is the rms sum of all of the spectral components except the fundamental and the ?st ?e harmonics. signal-to-noise + distortion ratio (sinad) sinad is the measured rms signal to rms sum of all other spectral components below the nyquist frequency, f s /2, excluding dc. effective number of bits (enob) the effective number of bits (enob) is calculated from the sinad data by: where: v corr = 0.5db. v corr adjusts the enob for the amount the input is below fullscale. total harmonic distortion (thd) thd is the ratio of the rms sum of the ?st 5 harmonic components to the rms value of the fundamental input signal. 2nd and 3rd harmonic distortion this is the ratio of the rms value of the applicable harmonic component to the rms value of the fundamental input signal. spurious free dynamic range (sfdr) sfdr is the ratio of the fundamental rms amplitude to the rms amplitude of the next largest spur or spectral component in the spectrum below f s /2. intermodulation distortion (imd) nonlinearities in the signal path will tend to generate intermodulation products when two tones, f 1 and f 2 , are present at the inputs. the ratio of the measured signal to the distortion terms is calculated. the terms included in the calculation are (f 1 + f 2 ), (f 1 - f 2 ), (2f 1 ), (2f 2 ), (2f 1 + f 2 ), (2f 1 -f 2 ), (f 1 +2f 2 ), (f 1 - 2f 2 ). the adc is tested with each tone 6db below full scale. transient response transient response is measured by providing a full-scale transition to the analog input of the adc and measuring the number of cycles it takes for the output code to settle within 12-bit accuracy. over-voltage recovery over-voltage recovery is measured by providing a full-scale transition to the analog input of the adc which overdrives the input by 200mv, and measuring the number of cycles it takes for the output code to settle within 12-bit accuracy. full power input bandwidth (fpbw) full power input bandwidth is the analog input frequency at which the amplitude of the digitally reconstructed output has decreased 3db below the amplitude of the input sinewave. the input sinewave has an amplitude which swings from -f s to +f s . the bandwidth given is measured at the speci?d sampling frequency. timing de?itions refer to figure 1, internal circuit timing, and figure 2, input-to-output timing, for these de?itions. aperture delay (t ap ) aperture delay is the time delay between the external sample command (the falling edge of the clock) and the time at which the signal is actually sampled. this delay is due to internal clock path propagation delays. aperture jitter (t aj ) aperture jitter is the rms variation in the aperture delay due to variation of internal clock path delays. data hold time (t h ) data hold time is the time to where the previous data (n - 1) is no longer valid. data output delay time (t od ) data output delay time is the time to where the new data (n) is valid. data latency (t lat ) after the analog sample is taken, the digital data is output on the bus at the third cycle of the clock. this is due to the pipeline nature of the converter where the data has to ripple through the stages. this delay is speci?d as the data latency. after the data latency time, the data representing each succeeding sample is output at the following clock pulse. the digital data lags the analog input sample by 3 clock cycles. enob = sinad + v corr -1.76 () /6.02, HI5805
12 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 HI5805

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